1. Field of the Invention
The present invention relates to a test system for a random access memory (RAM). The system according to the present invention is concerned with a RAM testing system which is provided with latch units at both the input side and the output side of the RAM. A measurement of the address access time by the widths of clock pulses can be carried out with a high precision.
2. Description of the Related Art
In general, in the prior art method of testing the access time of RAM's, signals are delivered to address input pins of a RAM from drivers of an LSI tester and the outputs of the RAM are fed to a comparator, thus implementing the measurement of the address access time. In this case the address inputs of the RAM are equivalent to a clock input of the latch when an input latch is provided.
In the conventional RAM testing system, the output of an oscillator is fed to each delay circuit and set signals are also delivered to the delay circuits to generate a clock signal No. 1, and a clock signal No. 2. The clock signal No. 1, is fed to input side flip-flop circuits and address signals are fed to the flip-flop circuits to send the output of the flip-flop circuits to the RAM elements to be tested. On the other hand, the clock signal No. 2 is fed to the output side flip-flop circuits. Each output of the output side flip-flop circuits is fed to comparators to which the expectation value is applied, respectively, and the outputs of the comparators are sent to a discriminator.
In the device of FIG. 1, two clock signals having different delay times are supplied to the input side flip-flop circuit and to the output side flip-flop circuit through the terminal pin PIN-A and through the terminal pin PIN-B, respectively.
Therefore, a problem arises in that an error occurs due to the difference in the timing of the signals through different terminal pins of the LSI tester, and an address access time of a RAM responsive to the clock pulse can not be accurately measured.